Radiation-Hardened VLSI SoC and RAM – Design Features for Bulk Silicon CMOS Technologies

Yuriy Gerasimov; Yaroslav Petrichkovich

doi:10.29039/2587-9936.2022.05.4.39

UDC

621.382.2/.3

RADIATION-HARDENED VLSI SOC AND RAM – DESIGN FEATURES FOR BULK SILICON CMOS TECHNOLOGIES Radiation-Hardened VLSI SoC and RAM – Design Features for Bulk Silicon CMOS Technologies

АА Аа

Published in Infocommunications and Radio Technologies · Pages 548–569 · Rubric: ELECTRONICS, PHOTONICS, INSTRUMENTATION AND COMMUNICATIONS (2.2)

DOI: https://doi.org/10.29039/2587-9936.2022.05.4.39

Received: 19.05.2022 Accepted: 05.06.2022 Published: 21.10.2022

Authors

Yuriy Gerasimov

ORCID

Yaroslav Petrichkovich

ORCID

Yuriy Gerasimov

Academic degree: candidate of technical sciences

SPC “Electronic Computing and Information Systems” (“ELVIS”), JSC Russian Federation · Moscow

ORCID

Yaroslav Petrichkovich

Academic degree: doctor of technical sciences

Science rang: professor

SPC “Electronic Computing and Information Systems” (“ELVIS”), JSC Russian Federation · Moscow

ORCID

ABSTRACT

The effect of various types of radiation and heavy nuclear particles on VLSI fabricated using CMOS technologies for bulk silicon at a level of 250–90 nm is analyzed. Developed and certified on test crystals (TC) are constructive-topological and circuit solutions for elements of digital libraries, complex-functional RAM blocks and peripheral mixed-signal blocks for designing radiation-hardened VLSI of the “system-on-chip” (SoC) type and RAM of category RT (products with an increased level of radiation resistance). The methodology of radiation-hardened by design (RHBD) has been further developed. For CAD tools, a design environment for VLSI of the RT category was created for manufacturing at Russian factories using available CMOS bulk technologies. Based on this design environment, competitive radiation-hardened high-performance processor CMOS VLSI SoC and VLSI RAM were created. Basic technical solutions are protected by RF patents.

KEYWORDS

bulk silicon, latch up, radiation hardness, radiation-hardened design, smart-functional block, VLSI system-on-a-chip, VLSI RAM, heavy nuclear particles

Funding

Rabota vypolnena za schet sobstvennyh sredstv AO NPC «ELVIS»

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GOST

Gerasimov Y. M., Petrichkovich Y. Y. Radiation-Hardened VLSI SoC and RAM – Design Features for Bulk Silicon CMOS Technologies // . 2022. pp. 548-569. DOI: https://doi.org/10.29039/2587-9936.2022.05.4.39. (Date of access 19.08.2026).

MLA

Yuriy Gerasimov, Petrichkovich Y. Y.. "Radiation-Hardened VLSI SoC and RAM – Design Features for Bulk Silicon CMOS Technologies." (2022): 548-569. DOI: https://doi.org/10.29039/2587-9936.2022.05.4.39.

APA

Gerasimov Y. M., Petrichkovich Y. Y. (2022). Radiation-Hardened VLSI SoC and RAM – Design Features for Bulk Silicon CMOS Technologies. , 548-569. https://doi.org/10.29039/2587-9936.2022.05.4.39

Chicago

Yuriy Gerasimov, Petrichkovich Y. Y.. "Radiation-Hardened VLSI SoC and RAM – Design Features for Bulk Silicon CMOS Technologies." , no. (2022): 548-569. https://doi.org/10.29039/2587-9936.2022.05.4.39.

WIKI

{{cite journal | author = Gerasimov Y. M., Petrichkovich Y. Y. | title = Radiation-Hardened VLSI SoC and RAM – Design Features for Bulk Silicon CMOS Technologies | journal = | year = 2022 | pages = 548-569 | doi = 10.29039/2587-9936.2022.05.4.39 }}

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RADIATION-HARDENED VLSI SOC AND RAM – DESIGN FEATURES FOR BULK SILICON CMOS TECHNOLOGIES Radiation-Hardened VLSI SoC and RAM – Design Features for Bulk Silicon CMOS Technologies

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