Moscow, Moscow, Russian Federation
Moscow, Moscow, Russian Federation
The effect of various types of radiation and heavy nuclear particles on VLSI fabricated using CMOS technologies for bulk silicon at a level of 250–90 nm is analyzed. Developed and certified on test crystals (TC) are constructive-topological and circuit solutions for elements of digital libraries, complex-functional RAM blocks and peripheral mixed-signal blocks for designing radiation-hardened VLSI of the “system-on-chip” (SoC) type and RAM of category RT (products with an increased level of radiation resistance). The methodology of radiation-hardened by design (RHBD) has been further developed. For CAD tools, a design environment for VLSI of the RT category was created for manufacturing at Russian factories using available CMOS bulk technologies. Based on this design environment, competitive radiation-hardened high-performance processor CMOS VLSI SoC and VLSI RAM were created. Basic technical solutions are protected by RF patents.
bulk silicon, latch up, radiation hardness, radiation-hardened design, smart-functional block, VLSI system-on-a-chip, VLSI RAM, heavy nuclear particles
1. A. Y. Nikiforov, V. A. Telets, and D. V. Boychenko, “Radiation Hardness Requirements - the Exotica for Gourmets or a Guarantee of the Design Result Success and High Technical Level for all Categories of Consumers?,” Nanoindustry Russia, pp. 39-41, 2018, doi:https://doi.org/10.22184/1993-8578.2018.82.39.41. (In Russ).
2. Y. M. Gerasimov, N. G. Grigoryev, A. V. Kobylyatskiy, Ya. Ya. Petrichkovich, and T. V. Solokhina, “Radiation-Hardening-By-Design of the High-Performance CMOS Nanometer System-on-chip,” Infocommunications and Radio Technologies, vol. 2, no. 1, pp. 33-51, 2019, doi:https://doi.org/10.15826/icrt.2019.02.1.04. (In Russ).
3. Yu. M. Gerasimov, N. G. Grigoryev, and Ya. Ya. Petrikovich, “Radiation Hardened by Design of Nanometer CMOS VLSI: Reality and Myths,” Nanoindustry Russia, vol. 13, no. 5s, pp. 319-324, Dec. 2020, doi:https://doi.org/10.22184/1993-8578.2020.13.5s.319.324. (In Russ).
4. Yu. M. Gerasimov, N. G. Grigoryev, A. V. Kobylyatskiy, Ya. Ya. Petrikovich, and T. V. Solokhina, “From the First CMOS Transistors to the Radiation-Hardened Nanometer CMOS Systems-on-Chip,” Nanoindustry Russia, vol. 13, no. 5s, pp. 268-274, 2019, doi:https://doi.org/10.22184/NanoRus.2019.12.89.268.274. (In Russ).
5. Radiation resistance of ECB products, / ed. A. I. Chumakov, Moscow: MEPhI, 2015. (In Russ).
6. A. I. Chumakov, Action of space radiation on integrated circuits, Moscow: Radio i svyaz’, 2004. (In Russ).
7. Yu. M. Gerasimov, N. G. Grigoryev, A. V. Kobylyatskiy, and Ya. Ya. Petrikovich, “Test Chips for Experiment-Based Radiation Hardness Calculation of Nanometer Systems-on-Chip,” Nanoindustry Russia, pp. 202-210, 2019, doi:https://doi.org/10.22184/NanoRus.2019.12.89.202.210. (In Russ).
8. Yu. M. Gerasimov, N. G. Grigoryev, A. V. Kobylyatskiy, and Ya. Ya. Petrikovich, pat. no. 2674415 (RF), “Radiation-resistant library of elements on complementary metal-oxide-semiconductor transistors, published in Bulletin of Inventions,” no. 34, 2018. (In Russ.).
9. D. A. Black, W. H. Robinson, I. Z. Wilcox, D. B. Limbrick, and J. D. Black, “Modeling of Single Event Transients With Dual Double-Exponential Current Sources: Implications for Logic Cell Characterization,” IEEE Transactions on Nuclear Science, vol. 62, no. 4, pp. 1540-1549, Aug. 2015, doi:https://doi.org/10.1109/tns.2015.2449073.
10. G. C. Messenger, “Collection of Charge on Junction Nodes from Ion Tracks,” IEEE Transactions on Nuclear Science, vol. 29, no. 6, pp. 2024-2031, Dec. 1982, doi:https://doi.org/10.1109/tns.1982.4336490.
11. M. J. Gadlage et al., “Single event transient pulse widths in digital microcircuits,” IEEE Transactions on Nuclear Science, vol. 51, no. 6, pp. 3285-3290, Dec. 2004, doi:https://doi.org/10.1109/tns.2004.839174.
12. J. A. Zoutendyk, L. S. Smith, G. A. Soli, and R. Y. Lo, “Experimental Evidence for a New Single-Event Upset (SEU) Mode in a CMOS SRAM Obtained from Model Verification,” IEEE Transactions on Nuclear Science, vol. 34, no. 6, pp. 1292-1299, 1987, doi:https://doi.org/10.1109/tns.1987.4337468.
13. Yu. M. Gerasimov, N. G. Grigoryev, A. V. Kobylyatskiy, Ya. Ya. Petrikovich, and D. K. Sergeev, “High-Speed Heavy-Ion Tolerant CMOS Logic Circuit Design Features,” Nanoindustry Russia, vol. 96, no. 3s, pp. 220-228, Jun. 2020, doi:https://doi.org/10.22184/1993-8578.2020.13.3s.220.228. (In Russ.).
14. Yu. M. Gerasimov, N. G. Grigoryev, A. V. Kobylyatskiy, and Ya. Ya. Petrikovich, patent no. 2692307 (RF). “Radiation-resistant memory element for static RAM based on complementary metal-oxide-semiconductor transistors,” published in Bulletin of Inventions, no 18, 2019. (In Russ).
15. Yu. M. Gerasimov, N. G. Grigoryev, A. V. Kobylyatskiy, and Ya. Ya. Petrikovich, “Radiation-Hardened CMOS SRAM 16MBIT 1657RY2Y,” Nanoindustry Russia, vol. 96, no. 3s, pp. 169-174, May 2020, doi:https://doi.org/10.22184/1993-8578.2020.13.3s.169.174. (In Russ.).
16. V. D. Baykov, Yu. M. Gerasimov, Ya. Ya. Petrikovich, and N. Yu. Rannev, pat. no. 2763038 (RF), “Voltage Controlled Complementary Metal Oxide Semiconductor (CMOS) Ring Oscillator Unit,” published in Bulletin of Inventions, no 36, 2022. (In Russ).
17. T. D. Loveless et al., “A Single-Event-Hardened Phase-Locked Loop Fabricated in 130 nm CMOS,” IEEE Transactions on Nuclear Science, vol. 54, no. 6, pp. 2012-2020, Dec. 2007, doi:https://doi.org/10.1109/tns.2007.908166.
